K4N56163QI-ZC2A

Product Summary

The 256Mb gDDR2 SDRAM chip K4N56163QI-ZC2A is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device achieves high speed graphic double-data-rate transfer rates of up to 500MHz for general applications. The K4N56163QI-ZC2A is designed to comply with the following key gDDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs of the K4N56163QI-ZC2A are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. A thirteen bit address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 256Mb(x16) device receives 13/9/2 addressing. The 256Mb gDDR2 device K4N56163QI-ZC2A is available in 84ball FBGAs(x16).

Parametrics

K4N56163QI-ZC2A absolute maximum dc ratings: (1)VDD, Voltage on VDD pin relative to Vss: - 1.0 V ~ 2.3 V; (2)VDDQ, Voltage on VDDQ pin relative to Vss: - 0.5 V ~ 2.3 V; (3)VDDL, Voltage on VDDL pin relative to Vss: - 0.5 V ~ 2.3 V ; (4)VIN, VOUT Voltage on any pin relative to Vss: - 0.5 V ~ 2.3 V; (5)TSTG, Storage Temperature: -55 to +100 ℃.

Features

K4N56163QI-ZC2A features: (1)1.8V + 0.1V power supply for device operation; (2)1.8V + 0.1V power supply for I/O interface; (3)4 Banks operation; (4)Posted CAS; (5)Programmable CAS Letency : 5,6 ,7; (6)Programmable Additive Latency : 0, 1, 2, 3 , 4, 5; (7)Write Latency (WL) = Read Latency (RL) -1; (8)Burst Legth : 4 and 8 (Interleave/nibble sequential); (9)Programmable Sequential/ Interleave Burst Mode; (10)Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature); (11)Off-chip Driver (OCD) Impedance Adjustment; (12)On Die Termination; (13)Refresh and Self Refresh Average Refresh Period 7.8us at lower than TCASE 85 ℃, 3.9us at 85 ℃ < TCASE < 95 ℃; (14)Lead Free 84 ball FBGA(RoHS compliant).

Diagrams