XC5VLX85T-1FFG1136C

Product Summary

The XC5VLX85T-1FFG1136C is an FPGA. The XC5VLX85T-1FFG1136C is available in -3, -2, -1 speed grades, with -3 having the highest performance. The XC5VLX85T-1FFG1136C contains many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO technology with built-in digitally-controlled impedance, ChipSync source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.

Parametrics

XC5VLX85T-1FFG1136C absolute maximum ratings: (1)VCCINT, Internal supply voltage relative to GND: –0.5 to 1.1 V; (2)VCCAUX, Auxiliary supply voltage relative to GND: –0.5 to 3.0 V; (3)VCCO, Output drivers supply voltage relative to GND: –0.5 to 3.75 V; (4)VBATT, Key memory battery backup supply: –0.5 to 4.05 V; (5)VREF, Input reference voltage: –0.5 to 3.75 V; (6)VIN: 3.3V I/O input voltage relative to GND(4) (user and dedicated I/Os): –0.75 to 4.05 V; 3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os): –0.95 to 4.4(Commercial Temperature) V; –0.85 to 4.3 (Industrial Temperature)V; 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os): –0.75 to VCCO + 0.5 V; (7)IIN: Current applied to an I/O pin, powered or unpowered: ±100 mA; Total current applied to all I/O pins, powered or unpowered: ±100 mA; (8)VTS: Voltage applied to 3-state 3.3V output (user and dedicated I/Os): –0.75 to 4.05 V; voltage applied to 3-state 2.5V or below output (user and dedicated I/Os): –0.75 to VCCO + 0.5 V; (9)TSTG, Storage temperature (ambient): –65 to 150 ℃; (10)TSOL, Maximum soldering temperature: +220 ℃; (11)TJ, Maximum junction temperature: +125 ℃.

Features

XC5VLX85T-1FFG1136C features: (1)Real 6-input look-up table (LUT) technology; (2)Dual 5-LUT option; (3)Improved reduced-hop routing; (4)64-bit distributed RAM option; (5)SRL32/Dual SRL16 option; (6)1.2 to 3.3V I/O Operation; (7)Source-synchronous interfacing using ChipSync technology; (8)Digitally-controlled impedance (DCI) active termination; (9)Flexible fine-grained I/O banking; (10)High-speed memory interface support; (11)65-nm copper CMOS process technology; (12)1.0V core voltage; (13)High signal-integrity flip-chip packaging available in standard or Pb-free package options; (14)FXT Platform only; (15)RISC architecture; (16)7-stage pipeline; (17)32-Kbyte instruction and data caches included; (18)Optimized processor interface structure (crossbar); (19)25 x 18, two’s complement, multiplication; (20)Optional adder, subtracter, and accumulator; (21)Optional pipelining; (22)Optional bitwise logical functionality; (23)Dedicated cascade connections.

Diagrams